1. Field of the Invention
The present invention relates to reducing the effects of digital circuit switching on sensitive circuitry and, in particular, to reducing the effects of the DC substrate offset produced by switching on and off digital circuit sections on sensitive analog circuit sections within the same integrated circuit.
2. Description of the Related Art
Integrated circuits (ICs) are typically formed in a manufacturing process on silicon wafers which provide a common substrate for the components of an IC. Several ICs are usually formed in each wafer, which is a very thin, flat disc typically about 8-12" in diameter at the present time. A group of ICs or wafers produced in a given manufacturing process are sometimes referred to as a "lot". During the manufacturing process, impurities are diffused into each silicon wafer to create transistors and other electronic components of the respective ICs of the wafer. These components are then interconnected through deposited metal layers to form logic or other functions. Once the wafer is completely processed, it is cut up into the individual die (chips), which are typically about 1/3" by 1/3" in size. Each die is mounted in a package and the terminals of the chip are connected to the package terminals through a wire bonding operation.
Each IC typically contains several distinct circuit portions or sections designed to perform various functions. So-called "mixed signal" ICs or chips provide both analog and digital circuit sections or functions on the same silicon die and thus on the common substrate in which they are formed. For example, a mixed signal IC may contain sensitive analog circuits such as op-amps, digital-to-analog converters (DACs) or analog-to-digital converters (ADCs), as well as a digital logic circuit section such as a digital signal processor (DSP). A typical mixed signal application, for example, involves taking an analog chip input and converting it to a digital word with an ADC. A DSP can then perform some complex mathematical algorithm on the digital representation of the analog data to create a digital output word. A DAC can then be used to convert the digital word from the DSP back to an analog signal, which is available at the chip output. The chip in this example may have unbalanced analog inputs and outputs on the order of hundreds of microvolts, in addition to digital control and data signals.
Because of the common substrate, various forms of noise can be communicated between circuit sections. The digital circuit sections typically generate more noise, and the analog circuit sections are typically more vulnerable to noise, primarily noise caused by the digital circuit sections. Digital circuits, for example, generate high frequencies and harmonics and other noise due, in part, to the sharp edges of the digital waveforms used for clock signals and the like. This digital circuit noise can be communicated to sensitive analog circuit sections through the common substrate and can adversely affect their operation.
One type of digital circuit noise is caused by switching a digital circuit or portion thereof on and off. This type of noise is sometimes referred to as digital switching noise. In a mixed signal IC, noise from the switching can also be communicated to analog circuit sections through the substrate. In addition to this type of noise, switching a digital circuit section on and off can introduce a DC offset into the substrate ground, causing the local substrate ground potential to fluctuate with respect to an external ground (the external ground which is the ground for the power supply of the digital circuit section being switched on and off). This can interfere with the operation of analog circuit sections, which produce output signals with reference to the local, substrate ground. This substrate or DC offset problem is described in further detail below.
Referring now to FIG. 1, there is shown a cross-sectional view of a mixed-signal integrated circuit (IC) 100. A circuit diagram illustrating the supply connections and resistances of IC 100 in further detail is shown in FIG. 2. As shown in FIG. 1, IC 100 comprises digital circuit and analog circuit sections, in a common P+ substrate. Input and output signals and power are connected from the package pins to the internal chip pins through several levels of interconnect. The signals, nodes, and resistances of IC 100 are labeled in FIGS. 1, 2 as follows: G.sub.NDA is the analog ground; V.sub.DDA is the analog supply voltage; G.sub.NDD is the digital ground; V.sub.DDD is the digital supply; D.sub.SUB is the digital circuit section substrate; A.sub.SUB is the analog circuit section substrate; R.sub.CM is the on-chip metallization resistance; R.sub.BW is the bond wire resistance; R.sub.PKG is the package lead resistance; R.sub.EPI is the P- epi layer resistance; and R.sub.SUB is the resistance of the substrate between D.sub.SUB and A.sub.SUB.
The connection of the chip digital and analog grounds to the PC board ground is a significant junction. The PC board is the external device containing the power supply that powers the digital circuit section. The PC board also contains the external ground (PC board ground) referenced by circuitry on the PC board, which receives output signals from components such as the analog output of the analog circuit section of IC 100.
Between the digital ground on the chip (G.sub.NDD) and the PC board ground there are several series resistances, as shown in FIG. 2. This includes the resistance of the on chip metallization (R.sub.CM) the bond wire resistance (R.sub.BW), and the resistance of the package lead (R.sub.PKG). Of these three, the bond wire resistance R.sub.BW is generally the most significant. The same holds true for the connection of the analog ground (G.sub.NDA) to the PC board.
Since both the digital and analog grounds G.sub.NDD, G.sub.NDA are connected to the substrate, there is also some resistive path therebetween (i.e., R.sub.EPI +R.sub.SUB +R.sub.EPI) through the shared substrate and the connecting epi layer portions. For a low resistivity substrate (which is common in today's IC processes) the digital and analog substrates, and hence the digital and analog grounds, are basically shorted together. Thus, the digital and analog circuit sections of an IC typically share a common, local ground.
Digital current (I.sub.DIGITAL) flows through the resistance between the local (digital chip) ground G.sub.NDD and the external (PC board) ground when the digital circuit section is "on," i.e. receiving power from the digital power supply on the PC board. This current flow of current I.sub.DIGITAL causes a voltage differential (IR drop) to exist between these two points. This causes the potential of the digital substrate D.sub.SUB to rise with respect to the PC (external) board ground, when the digital circuit section is on, which in turn causes the potential of the analog substrate A.sub.SUB (analog ground) to rise by approximately the same amount. For a digital current of 80 mA, for example, the substrate rise, or digital switching offset, with respect to the PC board ground, can be approximately 4 mV. The digital switching offset is introduced, therefore, into the local analog ground G.sub.NDA. Thus, any analog chip outputs, which are referenced to the analog chip ground G.sub.NDA, will also rise by 4 mV with respect to the board ground.
This digital switching offset may be introduced and removed often because various DC circuit sections are often switched on and off. Digital circuits are frequently switched off (put to "sleep") to save power, and are turned on again ("awaken") when they are needed. This may be done, for example, if the device comprising IC 100 and the PC board is battery-powered, in which case power usage is very important. Each power switch (i.e., from off to on, or from on to off) of the digital circuit section will cause D.sub.SUB and the digital ground G.sub.NDD, and thus A.sub.SUB and the analog ground G.sub.NDA, to shift either up or down by the digital switching offset, due to the change in I.sub.DIGITAL.
Thus, the local ground for analog circuit sections fluctuates with the digital switching offset each time the digital section is switched on or off. This change in the local ground potential by the offset amount in turn causes the analog outputs to shift by the approximately same amount (4 mV in the previous example).
Thus, this change in DC offset due to the digital circuit sections turning on and off can cause significant problems for the chip's analog inputs and outputs. For a 13 bit DAC output with a step size of 500 .mu.V (0.5 mV) this 4 mV offset amounts to 8 steps (8 LSB) of error, a significant amount. This problem becomes more common and more severe as system integration increases the desirability of mixing digital and analog functions on the same chip. The unwanted changes in analog output signals as digital circuits are switched on and off can be viewed as a special type or manifestation of digital switching noise, and may be referred to as digital switching offset noise.
Various techniques have been proposed and utilized to attempt to isolate noisy digital circuit sections from sensitive analog circuit sections within the same IC, to reduce some or all of the various noise problems caused by digital circuitry in a mixed signal chip. Such techniques include isolation by physical separation; isolation by separate supply rails; isolation by grounded guard rings/substrate trenches; differential circuitry in the sensitive analog section; use of low noise injecting digital circuitry, such as current steering logic; making the digital circuitry sections synchronous with the analog function and moving the clock edges away from critical analog sampling instances. Such conventional techniques, however, are not always sufficient or fully effective, or practical, feasible, or cost-effective to implement.
Conventional approaches geared specifically to minimizing the effects of digital switching noise, including digital switching offset noise, in addition to the foregoing techniques, include: careful isolation of the digital and analog sections; disconnecting grounds carrying switching current from the substrate to reduce the noise coupled to the substrate; using more ground pins to minimize the noise on the substrate; and using differential I/O (input/output) on sensitive analog signals so the common mode noise is canceled. The results of the isolation approach is technology dependent. With some technologies (such as a triple well process) the isolation can be fairly well accomplished; but these technologies are expensive. However, with a dual well process on a low resistivity substrate (which is common for many of today's CMOS fabrication processes), sufficient isolation is difficult to achieve. Disconnecting the grounds to separate the substrate ground from the switching ground requires a different layout methodology. This is inefficient from both an area and layout time perspective. The last two approaches (additional ground pins and differential I/O) are quite effective, but require additional package pins, which are often at a premium.